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nextpnr portable FPGA place and route tool

Language: C++

Look up the boards that use the Lattice ECP5 chips, I think these are the largest FPGAs that have a fully open toolchain: https://github.com/YosysHQ/nextpnr

You'd need to learn some digital design for any FPGA board. I recommend the book "Digital Design and Computer Architecture" by David and Sarah Harris.

this is true in general but

1) vivado webpack edition (ie free) lets you write (and flash) a bitstream for some of the small chips. i know it at least works for the artix-7 family because i'm doing it every day lately

2) for the artix-7 (and some lattice chips) you supposedly can use OSS (https://github.com/SymbiFlow/prjxray). i haven't tried it yet but one problem i can foresee is that the OSS tools won't infer stuff like brams and dsp. in fact the symbiflow people (i think?) explicitly call this out as the part of the project that's a work in progress.

some useful links:

https://arxiv.org/abs/1903.10407

https://github.com/YosysHQ/nextpnr

https://www.rapidwright.io/

There has been significant progress in reverse engineering bitstream formats of some FPGAs which has allowed the development of open source FPGA workflows. If you want to know more, take a look at:

Icestorm http://www.clifford.at/icestorm/

Yosys http://www.clifford.at/yosys/

NextPNR https://github.com/YosysHQ/nextpnr

SymbiFlow https://symbiflow.github.io/

For simulation and formal verification, yes, absolutely. Either Icarus Verilog, Verilator or SymbiYosys have been used for large commercial designs.

For synthesis, the only FPGAs families currently supported by an open source flow are the Lattice iCE40 and ECP5 [0]. The latter is something you can be decently productive with and can fit quite a bit of logic (think: Amiga reimplementation, PCIe interfacing, etc.).

If you'd like to port synthesizeable code from the open source world to the commercial world, this _should_ just work as long as you're willing to rewrite any physical interfacing code (since those depend on hardware blocks available in a particular family) and stick to high-quality Verilog. But that's the same as porting across any other FPGA families.

Disclaimer: I work with SymbioticEDA, who develop and provide commercial support for some open source digital logic tooling, like Yosys and Nextpnr.

[0] - https://github.com/YosysHQ/nextpnr

Verilator is an awesome tool. I suggest if you are interested in open-source EDA this you also check out Icarus Verilog [1] - an event based Verilog sim, Yosys [2] - a Verilog synthesis tool and formal solver, and NextPNR [3] - a place-and-route tool. The set of these provide a pretty reasonable set of tools for developing hardware (that is HDL) with fully open source software!

[1] - http://iverilog.icarus.com/ [2] - http://www.clifford.at/yosys/ [3] - https://github.com/YosysHQ/nextpnr

The site is actually a bit out of date, the ECP5 bit (Project Trellis) and nextpnr are already working:

https://github.com/YosysHQ/nextpnr