Not too happy with the "will be" part, because these types of endeavors are really hard, and it's unclear what likelihood of success the project has.

But apart from that ... I really wish these guys will be successful.

The FPGA world sorely needs to open up.

My favorite analogy is that the FPGA world (and the ASIC design world in general) needs a project equivalent to LLVM: something that sorts out once and for all all the gnarly and nasty low-level stuff, offering a consistent high level view of hardware (a hard feat of course, given how different H/W might be from one vendor or chip gen to the next, but LLVM did pull it off) - even if it's not as optimal as coding down to the metal would be - and lets the rest of the world build amazing, high-level tech. on top of it.

As a matter of fact, I really wish they had a link on their page to tell people how the project can be helped.

The site is actually a bit out of date, the ECP5 bit (Project Trellis) and nextpnr are already working:

https://github.com/YosysHQ/nextpnr