What does HackerNews think of vtr-verilog-to-routing?

full disclosure: I work for YosysHQ, who have an alternative open-source place-and-route program - [nextpnr](https://github.com/YosysHQ/nextpnr/) - and YosysHQ presently has [a grant](https://activities.esa.int/4000141380) from ESA on improving nextpnr.

to be blunt: nextpnr is what happens when you look at VPR as prior art and base every design decision around doing the opposite of VPR.

VPR is flexible, true: you can define an architecture description inside an XML file, but I view the VPR XML format to be poorly considered.

- commonly in an FPGA you will have "legality constraints" - for example, a block of LUTs cannot simultaneously be in carry-chain mode and act as LUT RAM. to produce a legal solution, all these constraints must be satisfied. to nextpnr this is [two basic](https://github.com/YosysHQ/nextpnr/blob/master/docs/archapi....) [API calls](https://github.com/YosysHQ/nextpnr/blob/master/docs/archapi....). to vpr, you must [walk the architecture](https://github.com/verilog-to-routing/vtr-verilog-to-routing...) to discover and cache legal placement positions. - VPR often requires significantly more detail about an FPGA than is easy to provide; for example, [how switchboxes are laid out](https://docs.verilogtorouting.org/en/latest/arch/reference/#...), or [routing metal resistance/capacitance](https://docs.verilogtorouting.org/en/latest/arch/reference/#...). to nextpnr, routing is just nodes and edges on a graph.

Further, VPR's algorithms tend not to be designed with performance in mind; simulated annealing as a placement method does not scale well past the tens of thousands of LUTs, which is why nextpnr moved from full simulated annealing to [heterogenous analytic placement](https://ieeexplore.ieee.org/document/6339278), and recently we have been working on a [multi-electrostatic placer](https://dl.acm.org/doi/abs/10.1145/3489517.3530568); both significantly more scalable methods based on using mathematical optimisation methods to place things nearby.

That is correct, VPR's placement is done using simulated annealing.

See section 8 of this paper (https://dl.acm.org/doi/pdf/10.1145/3388617), the originals VPR paper (https://link.springer.com/chapter/10.1007/3-540-63465-7_226), and the source code (https://github.com/verilog-to-routing/vtr-verilog-to-routing...) for more details.

Take a look at Verilog-to-Routing - an educational/research tool that is open-source.

https://github.com/verilog-to-routing/vtr-verilog-to-routing