Hopefully, EDA tools for chip-design will get similar attention too, as well as a "normal" CADs. Software like LibreCAD[1] and FreeCAD[2], Qucs[3], gEDA[4], Yosys[5] and Symbiflow[6], Chisel/FIRRTL[7], OpenROAD initiative[8], Degate[9], and many others.
[2] https://www.freecadweb.org/
[4] http://www.geda-project.org/
[5] http://www.clifford.at/yosys/
[6] https://symbiflow.github.io/
[7] https://www.chisel-lang.org/
Is there a high level overview, for programmers, of how chip design software works? Something I eventually want to investigate is building some of those pieces of software but I have no idea where to get started learning about that ecosystem. From a software perspective I have a good understanding of how source gets turned into machine code, which gets packaged into shared object code, which then gets linked into a binary. How do those steps work for HDLs? What standards are involved? How do you test that each of those steps works?
https://github.com/verilog-to-routing/vtr-verilog-to-routing