What does HackerNews think of ibex?

I definitely agree with the primary point, "building a chip that meets specfic requirements we got from the customer" is not easy and is what matters.

However, RISCV cores abound. In pretty much any HDL known to man with varying design trade-offs and capabilities. It's extremely difficult to differentiate at the RTL level at this time. Not impossible, but it would be a significant investment, which is I guess SiFive's business model. Sell IP at prices cheaper than that.

Here is a high quality, well documented, SystemVerilog version intended for embedded applications that I know has been included in multiple ASIC and FPGA designs successfully.

https://github.com/lowRISC/ibex

Of course these things never die, MIPS wont die. ARM wont die. Nobody is claiming they will. But also, you don't start very many a huge amount of new project with 8052s.

Performance isn't that important maybe (depends on the application), but energy often is, size is, having lots of vendors is, having a large software base is.

> So I'm really not sure how or why RISC-V would break into the uC world / low end.

If by lower end you mean 8-bit, then no it wont. But one of the large adopters of RISC-V are actually places where there used to be tiny 8-bit cores and now people want more substantial 32-bit cores and RISC-V is really good there.

And it has already broken into that market as there are already lots of RISC-V products shipping, lots of them in lots of consumer electronics from China.

RISC-V will continue to grow in that market, if you were a MIPS costumer for example, you are likely gone move on to RISC-V?

> If anywhere, they have a chance at the higher level, like at Rasp Pi level chips or stronger.

At the very low end being very cheap, not involving as many lawyers actually matters quite a bit because volumes are high. Specially when there are very competitive verified opensource cores as well.

Ibex: https://github.com/lowRISC/ibex

Used by Google in the OpenTitan Project

Open Hardware Group:

https://www.openhwgroup.org/

Chips Alliance:

https://www.chipsalliance.org

Not to mention all the commercial offerings (or commercial offerings that support those open-cores). They might not be open, but its easy to get up and running with RISC-V compared to commercial stuff.

There is just so much education moving to RISC-V. Lots of people will be educated in RISC-V and lots of people will look at some of these OpenSource cores to learn. When places like Berkley, Stanford and ETH embrace something it usually trickles down to most universities.

The pretty minimal RV32EC core Ibex is estimated 15k gates: https://github.com/lowRISC/ibex

But, the similarly minimal Arm Cortex M0 is, drumroll, 12k gates.

Not saying this means Arm is better than RISC-V, such a small difference can probably be explained by some microarchitectural feature or lack of it. Just that you can scale down Arm as well.

But yes, I can see tiny chips like these putting a squeeze on 8 and 16 bit microcontrollers.

We need a better list, but it would be quite some work to make it. I'd like a list of performance, size, implementation language and bus interfaces.

I've been looking at this one for high end (1.9 DMIPS/MHz!):

https://github.com/ultraembedded/biriscv

Google/lowRISC has this one:

https://github.com/lowRISC/ibex

I'm using picorv32 right now on Lattice ECP5- running code out of SPI-flash, but I added an instruction cache for speed.

It's amazing how many RISC-V things are happening all at once right now.

Anybody know of any free RISC-Vs with floating point? It would be helpful to have something similar to ARM Cortex-M4F.

Edit:

From the "riscv-cores-list" I see WARP-V, which I'm not interested in due to "TL-Verilog". But its FPU is this:

http://www.jhauser.us/arithmetic/HardFloat.html

So all of these RISC-Vs should have optional FPU support based on HardFloat :-) (not that I have any idea of the size of HardFloat).

It depends what you want to do? Do you want to build a processor from scratch? A basic processor for core RISC-V is actually quite simple. The RISC-V I specification (all the core instructions not including multi/div, none of the privileged spec) is not complex.

Implementing something like the story talks about is obviously far more complex.

If you're mostly interested in putting together existing processors that can again can vary in complexity, there are some things with 'batteries included' where you can just spin up an FPGA image that works then go poking around, others where there will be significant work in integrating things into a working system.

I'll give a plug to Ibex (https://github.com/lowRISC/ibex) which is the core I work on, it doesn't have an MMU and is targetted at embedded applications. It's a 'real' core, in that it's suitable for taping-out into a real system but still quite simple to understand. OpenTitan (https://github.com/lowRISC/opentitan) is a notable project we're also working on that uses it, it's an open source root of trust and will give you a working RISC-V SoC you can put on an FPGA, you can easily carve out the security things leaving you with a RISC-V core, some SRAM and various useful peripherals.