Cool work! Thanks for the article. It’s writeups like this that made me want to “upgrade” from emulating RISC-V in software to designing a core (I’ll try VHDL though).

I read this recently, might be helpful to see some of the choices (not all RiscV): https://justanotherelectronicsblog.com/?p=705

Edit: A list of riscv implementations: https://github.com/riscv/riscv-cores-list

I've been looking at this one for high end (1.9 DMIPS/MHz!):

https://github.com/ultraembedded/biriscv

Google/lowRISC has this one:

https://github.com/lowRISC/ibex

I'm using picorv32 right now on Lattice ECP5- running code out of SPI-flash, but I added an instruction cache for speed.

It's amazing how many RISC-V things are happening all at once right now.

Anybody know of any free RISC-Vs with floating point? It would be helpful to have something similar to ARM Cortex-M4F.

Edit:

From the "riscv-cores-list" I see WARP-V, which I'm not interested in due to "TL-Verilog". But its FPU is this:

http://www.jhauser.us/arithmetic/HardFloat.html

So all of these RISC-Vs should have optional FPU support based on HardFloat :-) (not that I have any idea of the size of HardFloat).