What does HackerNews think of riscv-bitmanip?
Working draft of the proposed RISC-V Bitmanipulation extension
You can already buy SOCs that support it, e.g. vision five 2 and star64.
Interestingly the risc-v vector extension [2] has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.
Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction [3].
[0] https://github.com/riscv/riscv-bitmanip
[1] https://github.com/riscv/riscv-profiles
[2] https://github.com/riscv/riscv-v-spec
[3] https://github.com/riscv/riscv-crypto/blob/master/doc/vector...
They're a proposal only (and I don't think they're an official proposal), and having read them it seems the guy just shoehorned in anything he could think of. I'm curious to see how much of it will be accepted.
Yeah, I like RISC-V generally, especially the base and the vector extension. However, they really went off the rails with the Bit Manipulation Extensions [1] still in draft form. Compare bfp which mixes control + data in the same register with ARMv8 bfi. It's only been added since the 0.92 draft but it seems to me very un-RISC-like.
https://github.com/riscv/riscv-bitmanip
Also conditional move which you really need for a lot of reasons but especially to avoid timing attacks in cryptography.
For instance the bit manipulation set at https://github.com/riscv/riscv-bitmanip adds frequently used operations like conditional move and population count, but also adds things like "multiply binary matrix" and "generalized or-combine", which I'm not sure even exists in X86 or AMD64.
Just can't live without that popcount.
The original title on this was "RISC-V Bitmanip Extension proposal is an education" because, besides a list of proposed instructions and precise definitions, the new draft explains in some detail how they are useful for real programs, and in many cases shows how they can be implemented with minimal additional gate count.
It's an education because many of these operations will be unfamiliar to most readers, and may suggest to them new ways to solve problems. Some of the instructions are also implemented in recent x86 cores, sometimes in an AVXx extension, but Intel's assembly language mnemonic offers little hint at how powerful it is, and its reference documentation sheds little more light.
So, previous drafts looked like a huge bolus of largely doubtful instructions that looked to bloat the RISC-V spec but be little used. Now we can see that most need only an extra gate here and there on such existing subunits as barrel shifters and multipliers, yet open up whole new vistas of operations they could be used for. The more powerful ones turn a whole family of O(N) operations (N the word size or number of 1s or 0s) to O(1). In turn, they are building blocks for fundamental signal analysis and encoding algorithms that may then run up to N times faster.
The document is maintained at https://github.com/riscv/riscv-bitmanip/ .