I’ve had a lot of fun learning RISC-V assembly off and on over the last year. I went through a colleague of mine’s tutorial series on implementing an operating system targeting RISC-V using Rust. Now I’m working on my own small assembler for RISC-V.

It’s been so much more fun to learn than x86!

Edit: link to the tutorial (http://osblog.stephenmarz.com/)

To me, a fun ISA is one which provides opportunities for golf, which basically means CISC ISAs with lots of different ways to do things. RISC-V is proudly, definitively not that and that's a good design decision, but you'll never be able to replace a stretch of straightforward code with a handful of more obscure opcodes and complicated addressing modes.

I'll always have SIMH.

The base ISA is very plain and RISCy. But I'd encourage you to go read the Bitmanip extension and find an opcode in there that doesn't have at least one obscure alternate use! =)

As for addressing modes, yeah I do wish we had a little bit more as a software person (but not as a hobby/toy cpu writer!). The current stuff can encode a surprising number of simple loops efficiently if you do it right, but of course if you come from x86 you'll have to do more with less...

They're a proposal only (and I don't think they're an official proposal), and having read them it seems the guy just shoehorned in anything he could think of. I'm curious to see how much of it will be accepted.