What does HackerNews think of skywater-pdk?
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
The open Skywater PDK is 130 nm : https://github.com/google/skywater-pdk (though I don't know how reliable the PDK is?)
Does your chip absolutely need a modern node? I'm assuming you've seen the open source skywater pdk, but here it is just in case. https://github.com/google/skywater-pdk
https://github.com/google/skywater-pdk
One could make an array of thermopiles, like the hacker that made their own imager out of discrete diodes (digiOBSCURA) . But each pixel would cost $7.
https://www.digikey.com/en/products/detail/excelitas-technol...
One might be able to make an array of thermistors (possibly with active cooling using a peltier) like the diycamera (digiOBSCURA) below. Might be an application of combining many RC oscillators in a tree and recovering the signal with an FFT. I have a gut feeling this is possible, but haven't show it. Isn't this the same as or similar to your keyboard multiplexer design?
https://www.digikey.com/en/products/detail/panasonic-electro...
https://github.com/IdleHandsProject/diycamera (digiOBSCURA)
One could experiment with microbolometers on tinytapeout. https://elicit.org/search?q=cmos+microbolometer
In OpenTitan we've built all the 'logical' IP ourselves from the ground up. This is the Verilog RTL you can see in our repository but you need the 'physical' IP to make a real chip. We haven't built any physical IP so we need to get it from the traditional industry sources which means traditional industry licensing (i.e. very much not open).
Since it's not clearly stated on the front page, I had to go digging to figure out what processes it supports. Looks like FreePDK45, which is "an open-source generic process design kit (PDK) (i.e., does not correspond to any real process and cannot be fabricated)" [0], ASAP7 "Warning Work in progress (not ready for use)" [1] and Skywater130 which "As of May 2020, this repository is targeting the SKY130 process node. If the SKY130 process node release is successful then in the future more advanced technology nodes may become available." [2] The floorplanner supports their ZeroSOC [3] which I guess is based on TitanSOC [4]
If this sounds negative, it's not, I just couldn't figure out what processes this was intended for without digging. ASAP7 is Arm and NCSU, and Skywater130 is Skywater and Google.
[0] https://github.com/mflowgen/freepdk-45nm [1] https://docs.siliconcompiler.com/en/latest/reference_manual/... [2] https://github.com/google/skywater-pdk [3] https://github.com/siliconcompiler/zerosoc [4] https://github.com/lowrisc/opentitan
There is eFabless, among other efforts in the vein you describe, they do a multi project wafer shuttle thing that google sponsors using skywater. It's supposedly an open source PDK, I haven't used it.
This is already false. The famous OpenPDK by Skywater (sponsored by Google) is proving this article wrong from the beginning. (https://github.com/google/skywater-pdk)
Yes, thats a rather old technology node, but you can now synthesize your free RISC-V design with a free Toolchain (openROAD) onto this open PDK.
Amazing times!
Raspberry Pi took advantage of the Google 130nm process: https://github.com/google/skywater-pdk, and came up with a visionary device. Sadly no RISC-V.
One effort to organize several previously available open source tools into a practical system is OpenLane, which is based on the DARPA OpenRoad project:
https://woset-workshop.github.io/PDFs/2020/a21.pdf
Recently, Google has financed a project where a foundry has made its data files available without any NDAs:
https://github.com/google/skywater-pdk
The combination has made it possible to have completely open source chip designs.
That is simply false. Maybe known to insiders at eFabless.
Seriously where do you see any public mention of "caravel" three months ago? There's absolutely nothing about it on the mailing lists [1] [2].
> it was announced at the start of the program
Where?
I heard about this in late July and have been following this very closely since they posted the design rules in early September. I've probably read through the DRC rule document more closely than anybody outside of Google/Skywater/eFabless. Two weeks ago there was nothing anywhere in any of that about having to use their "Caravel" management padframe.
As of 15-Sep (git commit 107103f922db43408f59a1540cd4bd3737b30172) the text "caravel" does not appear anywhere in the PDK [3]. I checked with:
$ find . -not -type d -exec grep -Hi caravel {} \;
[1] https://groups.google.com/d/forum/skywater-pdk-announce
Coming from a software background, my recommendation would be to come from above and work down towards the chips. The perfect route to take is to work with a soft RISC-V cpu running on an FPGA with a totally open toolchain. By utilizing open tools, you have the agency to both modify the tools for your own use, gaining knowledge into how the tools work as well as participating in the technology graph. As soon as you add even a minor feature to the tooling, you then have the ability to add features for other people. This makes you valuable and will open other opportunities.
Get a Lattice FPGA supported by Yosys [1] and learn Chisel [2] and Verilog [3] while working through Nand To Tetris [4]
Once you understand the hardware enough, those soft designs can start to be turned into hard designs using the Skywalker PDK [5] and get your Open Source designs made for free.
[1] http://www.clifford.at/yosys/
[2] https://www.chisel-lang.org/
[3] https://hackaday.io/project/160759-nand-to-tetris-in-verilog...
[4] https://www.nand2tetris.org/
[5] https://www.theregister.com/2020/07/03/open_chip_hardware/ https://github.com/google/skywater-pdk