I did a write up going over how to generate VGA video from scratch to produce some SNES like graphics:
https://gregchadwick.co.uk/blog/playing-with-the-pico-pt4/ https://gregchadwick.co.uk/blog/playing-with-the-pico-pt5/ https://gregchadwick.co.uk/blog/playing-with-the-pico-pt6/
> The PIO ports discussed here are on the order of 100kHz
PIO runs at the system clock, 125 MHz by default, overclocks of over 400 MHz have been reported stable. A single PIO can clock out 32 bits every cycle (with a DMA and a memory system that can feed this), giving you a total of 4 Gbps.
Running at full throttle like that, especially for a decent length of time is tricky if you want to actually do anything other than blast out bits but 16 or 8 bits per cycle is a lot more straight forward, so 2 or 1 Gbps.
DVI output has already been demonstrated, running two displays at 480p: https://github.com/Wren6991/picodvi
The DVI is maybe more of a party trick than something you'd do in production hardware but it does demonstrate how capable the PIO can be. You could happily implement the same concept in a more performant device and reach 10 Gbps or more in a reasonable way.
Each PIO is limited to 32 instruction words (16 bit words; the 5-bit address is baked into the instruction format so it can't be expanded without redesigning the ISA), its memory consists of some 4-word (32 bit word) FIFOs and two 32-bit scratch registers, and the instruction set is very limited. It can increment so you can do counted loops, but it has no ADD instruction, so e.g. it can't easily compute a packet checksum on its own, much less anything like an error correcting code. It is nice for basic bit banging of things like the Neopixel LED. Someone did DVI video with it (https://github.com/Wren6991/picodvi) but that was really stretching its capabilities, seemingly more of a flex than something really practical. Impressive though.
It's also odd that they used the M0+ core instead of an M3 or M4F, especially since they then bolted on an external divider/interpolator to speed up audio processing. Maybe future versions will upgrade. Perhaps even to risc-v ;).
I've been wondering whether the RPi foundation designed the PIO from scratch for this chip, or if it's an existing block they got from someplace. It strikes me as clunky and maybe old, coming from an era when transistors cost a lot more. As for the chip itself, it's always nice to have a new cheap MCU board, but it's hard to tell what they have in mind for it. A traditional single-core MCU would have been simpler and probably cheaper, and something aiming for more compute power would have been better off with more powerful cores (future versions might have that, and more cores too).
The coming ESP32c3 will supposedly be priced like the ESP8266 (i.e. $2 or so for a module) and it will have a RISC-V core and 300K of ram or something like that, plus wifi, so it in some ways seems more promising. For boards, I like the Longan Nano on seeedstudio, like a RISC-V based bluepill for $6 including a tiny TFT display. Unfortunately it has just 128KB of on-chip flash so it can't run micropython simply, but it has a microsd slot so maybe there is a way to use that.