What does HackerNews think of swerv_eh1?
A directory of Western Digital’s RISC-V SweRV Cores
Language:
SystemVerilog
For values of "now" equal to 2019
Western Digital announced an open source core ("SweRV") in 2019, so I assume they already use them now that we are a few years on from that announcement.
It's confusing that RISC-V is so often described as "open source". The specs (ISA + extensions) are open and free from patents (at least as far as we know). While there are a large number of open source implementations available, many of these, however, implement only a simple microcontroller-style RV32I core.
The cores available in "large" physical chips you can buy today (XuanTie C906 on the Allwinner D1 SoC, SiFive U54/74 e.g. on the BeagleV and HiFive Unmatched) are proprietary. I think one of the few companies that open sourced their commercially used cores is Western Digital ("swerv" cores - https://github.com/westerndigitalcorporation/swerv_eh1), but these are also RV32I microcontroller-class CPUs.
WD is a very active contributor to RISC-V, some of their "SweRV" RISC-V cores are open source: https://github.com/westerndigitalcorporation/swerv_eh1
There is a lot of open hardware, also a lot published by private companies.
See e.g.
https://ohwr.org/, https://opencores.org/
or https://github.com/westerndigitalcorporation/swerv_eh1_fpga https://github.com/westerndigitalcorporation/swerv_eh1