What does HackerNews think of fusesoc?

Introduction to FPGAs | Feb 2023

Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).

Show HN: Open-source, configurable HDMI output for FPGAs | Feb 2020

Thanks for this. You should look into getting this into the fusesoc repository, if possible.

https://github.com/olofk/fusesoc

How to set up Xilinx Vivado for source control | Nov 2019

Use fusesoc. https://github.com/olofk/fusesoc

Use your own editor and source control tools outside of Xilinx's 1990s straightjacket. It creates Vivado projects and invokes it to do synthesis. You can open the generated projects in Vivado if you really need their GUI.

Darpa invests $100M in a silicon compiler | Jun 2018

Expand Context ↕

Not sure what cores will be needed for you to break out the popcorn. But there are actually quite a few cores available under open and free licenses.

First off, the RISC-V community is based on the open ISA. There are several open implementations of the ISA. And the RISC-V community is meaking good headways in developing open tools, peripheral cores etc.

https://riscv.org/

Secondly there are at least two attempts at collecting and tracking open cores for FPGA- and ASIC-implementations.

LibreCores is the newer project. They have collected quite a few projects:

https://www.librecores.org/ https://www.librecores.org/project/list

Related to LibreCores is the SoC-builder and core package handler Fusesoc by Olof Kindgren. Fusesoc makes creating your SoC easy:

https://github.com/olofk/fusesoc

The older project is OpenCores. OpenCores has been quite tightly related to the OpenRISC CPU core, the wishbone set of on-chip interconnect solutions. They have been used in many FPGAs and ASICs

https://opencores.org/ https://openrisc.io/

Then you have projects like Cryptech that develops a complete, totally open, Hardware Security Module capable of doing certificate signing, OpenDNSSEC signing etc. The Cryptech Alpha design from PCB to FPGA cores and SW including pkcs11 handling is open. The project has amassed quite a few cores. The PCB design is available in kiCAD. (disclaimer: I'm part of the Cryptech core team doing a lot of the FPGA design work.)

https://cryptech.is/ https://trac.cryptech.is/wiki/GitRepositories

Speaking of tools like KiCAD, there are aqtually quite a few open tools for HW design. For simuation there are Icarus Verilog, Verilator, cver for example. They might not be as fast as VCS by Synoptsys. But they do work. I use them daily.

http://iverilog.icarus.com/ https://www.veripool.org/projects/verilator/wiki/Intro

For synthesis, P&R the state is less good. For implementation in Altera and Xilinx devices you currently have to use the cost free tools from the vendors. But there is work ongoing to reverse engineer Xilinx Spartan devices. I don't know the current state though.

But what has been reverse engineered are the ICE40 FPGA devices from Lattice. And for these you can use the open tool Yosys by Clifford Wolf (also mentioned below by someone else).

http://www.clifford.at/yosys/

And if you are looking for open implementations of crypto functions etc I have quite a few on Github and try to develop more all the time:

https://github.com/secworks

The sha256 and aes cores has been used in quite a few FPGA and ASIC designs. Right now I'm working on completing cores for the Blake2b and Blake2s hash functions.

I agree that we in the HW community is waay behind the SW community in terms of open tools, libraries (i.e. cores). But it is not totally rotten, and it is getting better. RISC-V is to me really exciting.