What does HackerNews think of Digital?

I'm more curious if there is something that makes visualizing the Verilog easier... for instance, I've done some small projects where I used Digital [0] (which is so unfortunately named, but awesome) to put blocks of Verilog into the visual representation and then connect my blocks together (like ALU, block ram, registers etc) and run simulation. But the problem is taking all that out back to Verilog and then doing my synthesis with Yosys is a manual chore.

I am wondering if there is some sorta... IDE that is letting people inspect projects with lots in individual Verilog files quickly and show the structure visually (and manage test benches run Icarus and GTK wave etc). I haven't seen this outside of vendor-specific tools like Xylinx's Vivado and I'm wondering if I am just missing something or if that kinda of IDE doesn't exist in any open source tools just yet.

[0] https://github.com/hneemann/Digital

Edit- and yes I get that I'm probably just not used to the management of Verilog codebases and it's no different than software packages with lots of 'modules' and you just work on a module at a time and it isn't that crazy. But I find it odd that there aren't at least some more viz tools, considering functions of a CPU are so 'block' based... I'd love to be able to load up the RTL folder of one of the CPU projects and see how all these Verilog modules are connected to one another and to the top level. Size of the busses, number of instances, etc. As though it were a Logisim project.

This is a game. Should you want a digital logic simulator that's not a game, check out https://github.com/hneemann/Digital.

Well logisim is dead, but evolution is a fork and then there's Digital https://github.com/hneemann/Digital which is I think a reimplementation of Logism's concepts?

I also hand designed a custom 16 bit CPU in logisim, because I was struggling to understand Nand2Tetris's HDL as well as I liked, and also because I stopped following the curriculum to go my own way. Logisim has a few hang ups, starting with a rather low upper bound on clock speed, completely single threaded simulation, and no process for PLL or similar clock multiplying strategies so if you want to do internal processor management or microcode based implementations, you will be stuck with an even lower fraction of that clock speed. The UI is slightly clunky by modern standards, debugging complicated circuits is less than fun, and the file format is less than great if you want to do anything more than no version control and only touching it with logisim