Other HDL based on scala includes SpinalHDL.
These two HDL are pretty welcomed because of opensource and usability. You can find lots of projects in them. Notably rocket-chip, which is also in chisel. https://github.com/chipsalliance/rocket-chip
They're around for a while but still young and some people are pushing for adoption.
The situation is slowly improving and there are various university research groups and corporations that have released larger amounts of open source code that one can use as a starting point:
- https://github.com/openhwgroup/cva6 (mostly done by ETHZ people initially, also see https://github.com/pulp-platform/pulpino)
- https://github.com/chipsalliance/Cores-SweRV-EL2 (one of several high quality open-source RISC-V cores by Western Digital)
- https://github.com/chipsalliance/rocket-chip (UCB by initial creators of RISC-V)
- https://github.com/electronicvisions/nux (POWER based embedded processor, that we have used in several neuromorphic chip tapeouts (silicon proven))
On the tooling side one great thing that happened is that the verilator open source simulator has gained a lot of traction.
- https://github.com/verilator/verilator
On the hardware synthesis side some exciting developments are also happening, mostly driven by the desire of companies like Google to be vendor independent for their Deep learning accelerator designs and through funding by DARPA.
https://github.com/chipsalliance/rocket-chip
So they picked a European rocket as a name.
My biased view is that iterative development with Chisel, to the point of functional verification, is going to be faster than in a traditional RTL language primarily because you have a robust unit testing framework for Scala (Scalatest) and a library for testing Chisel hardware, ChiselTest [^1]. Basically, adopting test driven development is zero-cost---most Chisel users are writing tests as they're designing hardware.
Note that there are existing options that help bridge this gap for Verilog/VHDL like VUnit [^2] and cocotb [^3].
For libraries, there's multiple levels. The Chisel standard library is providing basic hardware modules, e.g., queues, counters, arbiters, delay pipes, and pseudo-random number generators, as well as common interfaces, e.g., valid and ready/valid. Then there's an IP contributions repo (motivated by something like the old tensorflow contrib package) where people can add third-party larger IP [^4]. Then there's the level of standalone large IP built using Chisel that you can use like the Rocket Chip RISC-V SoC generator [^5], an OpenPOWER microprocessor [^6], or a systolic array machine learning accelerator [^7].
There are comparable efforts for building standard libraries in SystemVerilog, notably BaseJump STL [^8], though SystemVerilog's limited parameterization and lack of parametric polymorphism limit what's possible. You can also find lots of larger IP ready to use in traditional languages, e.g., a RISC-V core [^9]. Just because the user base of traditional languages is larger, you'll likely find more IP in those languages.
[^1]: https://github.com/ucb-bar/chisel-testers2
[^2]: https://vunit.github.io/
[^3]: https://docs.cocotb.org/en/latest/
[^4]: https://github.com/freechipsproject/ip-contributions
[^5]: https://github.com/chipsalliance/rocket-chip
[^6]: https://github.com/antonblanchard/chiselwatt
[^7]: https://github.com/ucb-bar/gemmini
(Coming from a Chisel/FIRRTL dev...) Couple of clarifying comments:
CDE[^1] is really a Rocket Chip[^2] specific design decision meant to suit the configuration needs of system-on-chip generation (or: it's a Scala library which actually doesn't depend on Chisel and could be useful in unrelated projects). Also, SiFive should have fixed the issues with exceptions a long while ago (stack traces are still a thing, though).
Chisel gets a lot of criticism due to the (necessary) complexities of Rocket Chip. However, don't let that dissuade you from using it for a separate digital design project. None of the Rocket Chip complexity comes into play there.
Compilation time is something that we really care about and are seeking to make better. Minute-long Verilog generation times are something you would only see for mammoth design like Rocket Chip (generating MBs of Verilog). Nonetheless, we have some ideas on how to improve this via actual optimizations or meta-optimizations like grouping compiler transformations together that are safe to do so.
We also are really trying to make the Verification easier. One of these is effort on better testing via "Testers2"[^3] (name is TBD). The second is on improving the readability of the generated Verilog, e.g., emission of case statements [^4], emission of else-if[^5] (now supported!), etc. If you have suggestions we'd be happy to take a look (code examples of "I got this, but I'd like that" would be a huge plus, too!).
Regardless, thanks for taking the time to check it out.
[^1]: https://github.com/chipsalliance/api-config-chipsalliance
[^2]: https://github.com/chipsalliance/rocket-chip
[^3]: https://github.com/ucb-bar/chisel-testers2
[^4]: https://github.com/freechipsproject/chisel3/issues/1198