tptacek

A way to do this more directly and without dealing with any assembly syntax and at a deeper level is to compile down to an emulation of a straightforward machine (I really like MSP430 for this), preferably to an emulator you write.

Having had the pleasure of writing a couple emulators and a couple compilers at this point: the emulator is easier than the compiler, by a lot. Relative to parsing and emitting code, emulating a straightforward architecture is easy.

This is a great post!

B4TMAN

Any reference(s) where I can read more about writing emulators?

carussell
Wirth came up with a simple RISC architecture for his compiler book. There's an emulator[1] for it, written by Peter De Wachter. Michael Schierl adapted Peter's emulator code into Java and JS. You can run it here:

http://schierlm.github.io/OberonEmulator/

I sent a bunch of patches to rework the in-browser emulator a couple weeks ago. If you don't know C, I recommend reading through the JS emulator's source. (View source should suffice—it's all unminified vanilla JS; there's no opinionated JS framework involved.)

With it running in the browser, the emulator frontend treats the web platform as its widget toolkit. The code to interface with that is in webdriver.js[2] and takes about 1000 lines of code. The CPU and memory operations themselves are implemented in risc.js[3] and only take about 1/3 that.

To follow along with instruction fetching/decoding/execution, you'll need to understand the ISA. There's a good 3-page overview linked from projectoberon.com under the title "RISC Architecture"[4]. A more in-depth description of the design is also available[5].

I have some tentative work for a machine-code level debugger online[6]. It's unfinished, however, so it comes with no documentation and the toolbar icons are missing. (There are tooltips, however.) So you can play with it if you feel like watching the registers and flags change while stepping through machine instructions.

1. https://github.com/pdewacht/oberon-risc-emu/

2. https://github.com/schierlm/OberonEmulator/blob/master/JS/we...

3. https://github.com/schierlm/OberonEmulator/blob/master/JS/ri...

4. https://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC...

5. https://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC...

6. https://www.colbyrussell.com/staging/aubergine/emu.html?imag...