Lots of issues with microcontrollers, even secure ones, can be found around the ISP routines. I remember issues with NXP Micros (also LPCs, but of another generation) where, if you glitch the power at just the right time, you can get it to ignore code readback protection.
I'm not sure that getting the manufacturers to open source the ROM code is the right solution, per se, as even if it was known beforehand that there was an issue here, you would still be left with the same solution space: disable the affected code paths, and prevent access to them with additional (external) integrity checking.
Voltage glitching is a serious but broadly orthogonal issue (and one that has a very different threat model than, say, a compromised software supply chain). We actually do believe that opening this ROM would have prevented the problem because it is in fact glaring -- and the demographic for these parts really cares about this! So it seems highly likely that this problem would have been found many times over, and certainly would have been found in an early rev of the part that would have allowed them to fix it in a subsequent mask.
We need open source ROMs (and open source firmware!), and we collectively need to stop finding excuses for vendors to not provide it.
The usual convincing argument comes in the form of large amounts of profit or lack there of along with liability waivers. Nothing else convinces companies faster. NXP is arguable one of the better micros to use as well, at least the Freescale derived parts.
No amount of pleading or finger pointing is likely to work.
Alternatively an open source asic based on open source cores and IP that you can have on an asic or fpga that people start having made in large quantities cutting out the middlemen might work as a serious spooky moment for the likes of microcontroller vendors.
I can see it happening, riscv and litex make it dead simple to create your own custom soc on an fpga, perhaps with custom accelerators or I/O functions. It’s really quite amazing.
Imagine taking a $7 or so max10 or lattice ice40 and rolling your own. No it’s not as efficient perhaps, but efficiency isn’t everything. Flexibility to correct things at a logic level, after the delivery, could be a godsend in some scenarios where difficulty in servicing or replacing hardware far exceeds the efficiency gains.
There’s also some neat new chips that combine a hard cpu core, some hard ip for bus interfaces, and pl. perhaps the best of all if the pl is easy to use and program with open tools. See quick logic for example.
FPGAs just have a different set of attack vectors. Maybe it's smaller and more esoteric, but they're not a silver bullet.
Agreed that they definitely aren't a silver bullet! We went pretty deep down the secure FPGA route -- they (such as there is more than one vendor, which there arguably isn't) are very, very proprietary. (Not only do you not have source code to ROMs, there are entire hidden cores!) Indeed, we ultimately abandoned that route for quotidian reasons: we couldn't get their proprietary toolchain to work reliably on a Linux box, and we were getting the runaround. Our belief was that if their support was so bad on something so simple, it was going to be much worse when we found more serious issues with the device. Our view was (and is) that open FPGAs are a necessary (but not sufficient) step to get us to secure FPGAs.
https://www.crowdsupply.com/sutajio-kosagi/precursor
They are trying to have an hardware platform that can be inspected and it is based on an FPGA with a RISC-V Softcore.
Its by Bunnie, and he great talks about the choices and why he made them:
Keynote: Precursor - Trustable Open Hardware for Everyday Use - Bunnie Huang (https://www.youtube.com/watch?v=Fw5FEuGRrLE)
They are also doing their own Rust Message passing OS called Xous that might be of interest.